The present invention relates to digital microprocessors, and in particular but not exclusively, to microprocessors configurable to repeat program flow.
Many different types of processors are known, of which microprocessors are but one example. For example, Digital Signal Processors (DSPs) are widely used, in particular for specific applications, such as mobile processing applications. DSPs are typically configured to optimize the performance of the applications concerned and to achieve this they employ more specialized execution units and instruction sets. Particularly in, but not exclusively, applications such as mobile telecommunications applications, it is desirable to provide ever increasing DSP performance while keeping power consumption as low as possible.
In a DSP or microprocessor, machine-readable instructions stored in a program memory are sequentially executed by the processor in order for the processor to perform operations or functions. The sequence of machine-readable instructions is termed a xe2x80x9cprogramxe2x80x9d. Although the program instructions are typically performed sequentially, certain instructions permit the program sequence to be broken, and for the program flow to repeat a block of instructions. Such repetition of a block of instructions is known as xe2x80x9clooping,xe2x80x9d and the block of instructions are known as a xe2x80x9cloopxe2x80x9d or a xe2x80x9cblock.xe2x80x9d
In order to reduce power consumption, many microprocessors provide a low power mode in which the clock is slowed during times of inactivity, or certain peripheral devices are turned off when not needed. The processor may enter an xe2x80x9cidlexe2x80x9d mode or a xe2x80x9csleepxe2x80x9d mode until an interrupt occurs to restart full operation.
The present invention is directed to further reducing power consumption by microprocessors such as, for example but not exclusively, digital signal processors.
Aspects of the invention are specified in the claims. In accordance with a first aspect of the invention there is provided a method for operating a digital system that includes a microprocessor. A portion of the microprocessor is partitioned into a plurality of partitions. The microprocessor executes a sequence of instructions within an instruction pipeline of the microprocessor, and repetitively executes a block of instructions within the sequence of instructions. It is determined that at least one of the plurality of partitions is not needed to execute the block of instructions. In order to reduce power dissipation, operation of the unneeded partition(s) is inhibited while the block of instructions is repetitively executed.
In accordance with a second aspect of the invention, a repeat profile parameter is provided which is indicative of the partition(s) not needed to execute of the block of instructions.
In accordance with another aspect of the invention, the repeat profile parameter is provided by an instruction executed prior to the block of instructions.
In accordance with another aspect of the invention, the repeat profile parameter is determined by monitoring execution of a first iteration of the block of instructions and thereby deriving the repeat profile parameter.
In accordance with another aspect of the invention, separate repeat profile parameters are provided for an inner loop and an outer loop.
In accordance with another aspect of the invention, an interrupt during execution of the block of instructions causes masking of the partition inhibition so that all partitions of the microprocessor are enabled during execution of the ISR and unmasking of partition inhibition when returning to repetitive execution of the block of instructions after execution of the ISR is completed.
In accordance with other aspects of the invention, various portions of the microprocessor can be partitioned and partially inhibited during execution of a block of instructions. For example, the instruction decoder is partitioned according to groups -of instructions. The instruction register is partitioned according to various instruction lengths. The instruction pipeline is partitioned according to parallel instruction execution. A portion of the microprocessor is partitioned according to data types. Address generation circuitry is partitioned according to address modes. Status circuitry is inhibited if not required during execution of the block of instructions.
In another aspect of the invention there is provided a method for assembling a source code program to create a sequence of instructions, wherein the sequence of instructions has a repeatable block of instructions including an initial instruction and a final instruction. An instruction table is created with an entry for each instruction executable by a selected microprocessor, such that the entry for each instruction includes a group pattern defining a group of instructions that includes that instruction. The source code is transformed into a sequence of instructions, and the initial instruction and the final instruction is determined for a repeatable block of instructions associated with a prologue instruction. A plurality of group patterns selected from the instruction table representative of each instruction in the block of instructions is combined to form a repeat profile parameter, and the repeat profile parameter is associated with the prologue instruction in the sequence of instructions.
In accordance with an aspect of the present invention, partitioning of the instruction decoder for several instruction groups allows one or more of the decoder partitions to remain idle during execution of an instruction loop. Consequently, there is a corresponding reduction in power consumption by the microprocessor.
Therefore, embodiments of the invention are particularly suitable for use in portable apparatus, such as wireless communication devices. Typically such a wireless communication device comprise a user interface including a display such as liquid crystal display or a TFT display, and a keypad or keyboard for inputting data to the communications device. Additionally, a wireless communication device will also comprise an antenna for wireless communication with a radio telephone network or the like.